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    • elf2mif

      Public
      Utility to convert an ELF file into a Memory Initialization File (MIF)
      C++
      BSD 2-Clause "Simplified" License
      0000Updated Aug 30, 2023Aug 30, 2023
    • cv32e40p

      Public
      CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
      SystemVerilog
      Other
      415000Updated Feb 18, 2021Feb 18, 2021
    • Documentation for the OpenHW Group's set of CORE-V RISC-V cores
      Python
      Other
      96000Updated Oct 5, 2020Oct 5, 2020
    • riscv-dbg

      Public
      RISC-V Debug Support for our PULP Cores
      SystemVerilog
      Other
      72000Updated Jul 23, 2020Jul 23, 2020
    • Python's excellent OptionParser in C++
      C++
      MIT License
      48000Updated Apr 9, 2020Apr 9, 2020
    • ELFIO

      Public
      ELFIO - ELF (Executable and Linkable Format) reader and producer implemented as a header only C++ library
      C++
      MIT License
      157000Updated Apr 9, 2020Apr 9, 2020
    • C
      GNU General Public License v2.0
      21000Updated Aug 1, 2019Aug 1, 2019
    • Spike, a RISC-V ISA Simulator
      C
      Other
      844000Updated Sep 26, 2018Sep 26, 2018
    • A mirror of the upstream binutils-gdb repository for ARC specific work
      C
      GNU General Public License v2.0
      10000Updated Jul 21, 2016Jul 21, 2016
    • gcc

      Public
      The development tree for GCC for the Synopsys DesignWare ARC processor family
      C
      GNU General Public License v2.0
      14000Updated Jul 21, 2016Jul 21, 2016
    • toolchain

      Public
      Repository containing releases of prebuilt GNU toolchains for DesignWare ARC Processors from Synopsys (available from 'releases' link below). The repository itself contains all the scripts required to build the GNU toolchain. Toolchain documentation available at https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/wiki . Processor I…
      Shell
      GNU General Public License v3.0
      48000Updated Jul 13, 2016Jul 13, 2016