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Remove AsmLabel.
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@sisshiki1969
sisshiki1969 committed Sep 19, 2024
1 parent d0a77dd commit 1b123ba
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Showing 4 changed files with 125 additions and 160 deletions.
86 changes: 33 additions & 53 deletions monoruby/src/compiler/jitgen.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -42,10 +42,6 @@ struct JitContext {
///
basic_block_labels: HashMap<BasicBlockId, DestLabel>,
///
/// Destination labels for AsmLabels.
///
asm_labels: Vec<Option<DestLabel>>,
///
/// Basic block information.
///
bb_scan: Vec<(ExitType, SlotInfo)>,
Expand Down Expand Up @@ -102,11 +98,11 @@ struct JitContext {
///
/// Information for bridges.
///
bridges: Vec<(AsmIr, AsmLabel, BasicBlockId)>,
bridges: Vec<(AsmIr, DestLabel, BasicBlockId)>,
///
/// Information for continuation bridge.
///
continuation_bridge: Option<(Option<ContinuationInfo>, AsmLabel)>,
continuation_bridge: Option<(Option<ContinuationInfo>, DestLabel)>,
///
/// Class version at compile time.
///
Expand All @@ -124,13 +120,6 @@ struct JitContext {
start_codepos: usize,
}

impl std::ops::Index<AsmLabel> for JitContext {
type Output = DestLabel;
fn index(&self, index: AsmLabel) -> &Self::Output {
self.asm_labels[index.0].as_ref().unwrap()
}
}

#[derive(Debug)]
struct BackedgeInfo {
target_ctx: MergeContext,
Expand Down Expand Up @@ -159,9 +148,6 @@ impl std::ops::Index<BcIndex> for Incoming {
}
*/

#[derive(Clone, Copy, Debug)]
struct AsmLabel(usize);

impl JitContext {
///
/// Create new JitContext.
Expand All @@ -184,7 +170,6 @@ impl JitContext {
let local_num = func.local_num();
Self {
basic_block_labels,
asm_labels: vec![],
bb_scan,
loop_backedges: HashMap::default(),
loop_info: HashMap::default(),
Expand All @@ -206,12 +191,6 @@ impl JitContext {
}
}

fn asm_label(&mut self) -> AsmLabel {
let label = AsmLabel(self.asm_labels.len());
self.asm_labels.push(None);
label
}

///
/// Add new branch from *src_idx* to *dest* with the context *bbctx*.
///
Expand All @@ -221,7 +200,7 @@ impl JitContext {
src_idx: BcIndex,
dest: BasicBlockId,
mut bbctx: BBContext,
branch_dest: AsmLabel,
branch_dest: DestLabel,
) {
bbctx.sp = func.get_sp(src_idx);
#[cfg(feature = "jit-debug")]
Expand All @@ -243,7 +222,7 @@ impl JitContext {
src_idx: BcIndex,
dest: BasicBlockId,
mut bbctx: BBContext,
branch_dest: AsmLabel,
branch_dest: DestLabel,
) {
bbctx.sp = func.get_sp(src_idx);
#[cfg(feature = "jit-debug")]
Expand Down Expand Up @@ -280,15 +259,15 @@ impl JitContext {

fn compile_bb(
&mut self,
codegen: &mut Codegen,
store: &Store,
func: &ISeqInfo,
position: Option<BytecodePtr>,
bbid: BasicBlockId,
) -> AsmIr {
let mut ir = AsmIr::new();
ir.inst
.push(AsmInst::BasicBlockLabel(self.basic_block_labels[&bbid]));
let mut bb = if let Some(bb) = self.target_ctx.remove(&bbid) {
ir.inst.push(AsmInst::Label(self.basic_block_labels[&bbid]));
let mut bbctx = if let Some(bb) = self.target_ctx.remove(&bbid) {
bb
} else if let Some(bb) = self.incoming_context(&mut ir, func, bbid) {
self.gen_continuation(&mut ir);
Expand All @@ -300,29 +279,29 @@ impl JitContext {
};

let BasciBlockInfoEntry { begin, end, .. } = func.bb_info[bbid];
for bb_pos in begin..=end {
ir.bc_index(bb_pos);
bb.next_sp = func.get_sp(bb_pos);
for bc_pos in begin..=end {
ir.bc_index(bc_pos);
bbctx.next_sp = func.get_sp(bc_pos);

match self.compile_inst(&mut ir, &mut bb, store, func, bb_pos) {
match self.compile_inst(codegen, &mut ir, &mut bbctx, store, func, bc_pos) {
CompileResult::Continue => {}
CompileResult::Exit => return ir,
CompileResult::Recompile => {
let pc = func.get_pc(bb_pos);
ir.recompile_and_deopt(&mut bb, pc, position);
let pc = func.get_pc(bc_pos);
ir.recompile_and_deopt(&mut bbctx, pc, position);
return ir;
}
CompileResult::Break => break,
}

ir.clear(&mut bb);
bb.sp = bb.next_sp;
ir.clear(&mut bbctx);
bbctx.sp = bbctx.next_sp;
}

let next_idx = end + 1;
if let Some(next_bbid) = func.bb_info.is_bb_head(next_idx) {
let label = self.asm_label();
self.new_continue(func, end, next_bbid, bb, label);
let label = codegen.jit.label();
self.new_continue(func, end, next_bbid, bbctx, label);
if let Some(target_ctx) = self.incoming_context(&mut ir, func, next_bbid) {
self.gen_continuation(&mut ir);
assert!(self.target_ctx.insert(next_bbid, target_ctx).is_none());
Expand All @@ -333,6 +312,7 @@ impl JitContext {

fn compile_inst(
&mut self,
codegen: &mut Codegen,
ir: &mut AsmIr,
bbctx: &mut BBContext,
store: &Store,
Expand Down Expand Up @@ -676,7 +656,7 @@ impl JitContext {
brkind,
} => {
let index = bc_pos + 1;
let branch_dest = self.asm_label();
let branch_dest = codegen.jit.label();
let deopt = ir.new_deopt(bbctx, pc);
let mode = ir.fmode(&mode, bbctx, lhs_class, rhs_class, deopt);
ir.unlink(bbctx, dst);
Expand All @@ -692,7 +672,7 @@ impl JitContext {
brkind,
} => {
let index = bc_pos + 1;
let branch_dest = self.asm_label();
let branch_dest = codegen.jit.label();
ir.fetch_fixnum_binary(bbctx, pc, &mode);
ir.unlink(bbctx, dst);
ir.clear(bbctx);
Expand All @@ -708,7 +688,7 @@ impl JitContext {
..
} => {
let index = bc_pos + 1;
let branch_dest = self.asm_label();
let branch_dest = codegen.jit.label();
ir.fetch_binary(bbctx, mode);
ir.unlink(bbctx, dst);
ir.clear(bbctx);
Expand Down Expand Up @@ -930,36 +910,36 @@ impl JitContext {
ir.inst.push(AsmInst::EnsureEnd);
}
TraceIr::Br(dest_idx) => {
self.gen_branch(ir, bbctx, func, bc_pos, dest_idx);
self.gen_branch(codegen, ir, bbctx, func, bc_pos, dest_idx);
return CompileResult::Exit;
}
TraceIr::CondBr(cond_, dest_idx, false, brkind) => {
if bbctx.is_truthy(cond_) {
if brkind == BrKind::BrIf {
self.gen_branch(ir, bbctx, func, bc_pos, dest_idx);
self.gen_branch(codegen, ir, bbctx, func, bc_pos, dest_idx);
return CompileResult::Exit;
}
} else if bbctx.is_falsy(cond_) {
if brkind == BrKind::BrIfNot {
self.gen_branch(ir, bbctx, func, bc_pos, dest_idx);
self.gen_branch(codegen, ir, bbctx, func, bc_pos, dest_idx);
return CompileResult::Exit;
}
} else {
let branch_dest = self.asm_label();
let branch_dest = codegen.jit.label();
ir.fetch_to_reg(bbctx, cond_, GP::Rax);
ir.inst.push(AsmInst::CondBr(brkind, branch_dest));
self.new_branch(func, bc_pos, dest_idx, bbctx.clone(), branch_dest);
}
}
TraceIr::NilBr(cond_, dest_idx) => {
let branch_dest = self.asm_label();
let branch_dest = codegen.jit.label();
ir.fetch_to_reg(bbctx, cond_, GP::Rax);
ir.inst.push(AsmInst::NilBr(branch_dest));
self.new_branch(func, bc_pos, dest_idx, bbctx.clone(), branch_dest);
}
TraceIr::CondBr(_, _, true, _) => {}
TraceIr::CheckLocal(local, dest_idx) => {
let branch_dest = self.asm_label();
let branch_dest = codegen.jit.label();
ir.fetch_to_reg(bbctx, local, GP::Rax);
ir.inst.push(AsmInst::CheckLocal(branch_dest));
self.new_branch(func, bc_pos, dest_idx, bbctx.clone(), branch_dest);
Expand All @@ -973,7 +953,7 @@ impl JitContext {
} => {
let else_idx = dest_bb[0];
for bbid in dest_bb {
let branch_dest = self.asm_label();
let branch_dest = codegen.jit.label();
self.new_branch(func, bc_pos, bbid, bbctx.clone(), branch_dest);
}
let deopt = ir.new_deopt(bbctx, pc);
Expand All @@ -987,13 +967,14 @@ impl JitContext {

fn gen_branch(
&mut self,
codegen: &mut Codegen,
ir: &mut AsmIr,
bb: &mut BBContext,
func: &ISeqInfo,
bc_pos: BcIndex,
dest: BasicBlockId,
) {
let branch_dest = self.asm_label();
let branch_dest = codegen.jit.label();
ir.inst.push(AsmInst::Br(branch_dest));
self.new_branch(func, bc_pos, dest, bb.clone(), branch_dest);
}
Expand Down Expand Up @@ -1032,7 +1013,7 @@ struct BranchEntry {
/// context of the source basic block.
bbctx: BBContext,
/// `DestLabel` for the destination basic block.
branch_dest: AsmLabel,
branch_dest: DestLabel,
/// true if the branch is a continuation branch.
/// 'continuation' means the destination is adjacent to the source basic block on the bytecode.
cont: bool,
Expand Down Expand Up @@ -1138,7 +1119,6 @@ impl BBContext {
for BranchEntry {
src_idx: _src_idx,
bbctx,
branch_dest: _,
..
} in entries.iter()
{
Expand Down Expand Up @@ -1309,7 +1289,7 @@ impl Codegen {
#[cfg(feature = "jit-debug")]
eprintln!(" new_branch_init: {}->{}", BcIndex(0), start_pos);
let bb_begin = func.bb_info.get_bb_id(start_pos);
let branch_dest = ctx.asm_label();
let branch_dest = self.jit.label();
ctx.branch_map.insert(
bb_begin,
vec![BranchEntry {
Expand All @@ -1330,7 +1310,7 @@ impl Codegen {

let mut bbir = vec![];
for bbid in bb_begin..=bb_end {
let ir = ctx.compile_bb(store, func, position, bbid);
let ir = ctx.compile_bb(self, store, func, position, bbid);
bbir.push((bbid, ir));
}

Expand Down
29 changes: 12 additions & 17 deletions monoruby/src/compiler/jitgen/asmir.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -677,7 +677,7 @@ impl AsmIr {
mode: OpMode,
kind: CmpKind,
brkind: BrKind,
branch_dest: AsmLabel,
branch_dest: DestLabel,
) {
self.inst.push(AsmInst::IntegerCmpBr {
mode,
Expand All @@ -692,7 +692,7 @@ impl AsmIr {
mode: FMode,
kind: CmpKind,
brkind: BrKind,
branch_dest: AsmLabel,
branch_dest: DestLabel,
) {
self.inst.push(AsmInst::FloatCmpBr {
mode,
Expand Down Expand Up @@ -1101,10 +1101,10 @@ pub(super) enum AsmInst {
Raise,
MethodRet(BytecodePtr),
EnsureEnd,
Br(AsmLabel),
CondBr(BrKind, AsmLabel),
NilBr(AsmLabel),
CheckLocal(AsmLabel),
Br(DestLabel),
CondBr(BrKind, DestLabel),
NilBr(DestLabel),
CheckLocal(DestLabel),
///
/// Conditional branch
///
Expand All @@ -1115,7 +1115,7 @@ pub(super) enum AsmInst {
///
GenericCondBr {
brkind: BrKind,
branch_dest: AsmLabel,
branch_dest: DestLabel,
},
OptCase {
max: u16,
Expand Down Expand Up @@ -1287,7 +1287,7 @@ pub(super) enum AsmInst {
mode: OpMode,
kind: CmpKind,
brkind: BrKind,
branch_dest: AsmLabel,
branch_dest: DestLabel,
},
FloatCmp {
kind: CmpKind,
Expand All @@ -1297,7 +1297,7 @@ pub(super) enum AsmInst {
kind: CmpKind,
mode: FMode,
brkind: BrKind,
branch_dest: AsmLabel,
branch_dest: DestLabel,
},

GuardBaseClass {
Expand Down Expand Up @@ -1505,8 +1505,7 @@ pub(super) enum AsmInst {

#[allow(dead_code)]
BcIndex(BcIndex),
Label(AsmLabel),
BasicBlockLabel(DestLabel),
Label(DestLabel),
}

impl AsmInst {
Expand Down Expand Up @@ -1616,7 +1615,7 @@ impl Codegen {
ir: AsmIr,
store: &Store,
ctx: &mut JitContext,
entry: Option<AsmLabel>,
entry: Option<DestLabel>,
exit: Option<BasicBlockId>,
) {
#[cfg(feature = "emit-asm")]
Expand All @@ -1641,15 +1640,11 @@ impl Codegen {
}
}

for label in ctx.asm_labels.iter_mut().filter(|i| i.is_none()) {
*label = Some(self.jit.label());
}

if exit.is_some() {
self.jit.select_page(1);
}
if let Some(entry) = entry {
self.jit.bind_label(ctx[entry]);
self.jit.bind_label(entry);
}

#[cfg(feature = "emit-asm")]
Expand Down
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